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MagnaChip to Offer Cost Competitive Redistribution Layer Metal Process and Copper Wire Bonding
Date : 2011/12/12


MagnaChip to Offer Cost Competitive Redistribution Layer Metal Process and Copper Wire Bonding

 

SEOUL, South Korea and CUPERTINO, Calif., Dec. 12, 2011 - MagnaChip Semiconductor Corporation ("MagnaChip Semiconductor") (NYSE: MX), a Korea-based designer and manufacturer of analog and mixed signal semiconductor products, today announced that it now offers a redistribution layer (RDL) metal process for wafer bumping and an IO structure and process that is fully compatible with copper wire bonding. This process is designed to reduce semiconductor packaging costs while meeting the specialized application needs of foundry customers.

The redistribution layer metal process converts wire bond pads at the perimeter of the die to an array of bump pads that are relocated to the center area of the die. The relocation of pads allows for a larger pad pitch for wafer bumping making it possible to use low cost solder bumps instead of plated bumps. The redistributed bond pad process has recently found its way into other advanced packaging methodologies such as wafer-level chip-scale packaging, system-in-package, and 3-D packaging. This process requires one additional aluminum layer and is fully compatible with MagnaChip's standard CMOS process.

Related to packaging trends, copper versus gold wire bonding has become one of the preferred methods for semiconductor interconnection because of its cost and performance features. Copper is a lower cost alternative to gold for packaging applications and has higher electrical and thermal conductivity making copper wire an excellent bonding material. In addition, copper bonds have greater reliability at elevated temperatures than gold bonds because of its lower tendency to form intermetallic compounds. One of the major challenges of copper wire bonding had been the significant mechanical stress imposed on bonding pads. This stress often resulted in dielectric cracks beneath the pads. MagnaChip resolved this issue in cooperation with the major packaging companies, including Amkor.

T.J. Lee, Senior Vice President and General Manager of MagnaChip's Corporate Engineering stated, "We are very pleased to announce the offering of cost competitive backend processes such as the redistribution layer metal process and copper wire bonding. Our goal is to continue to develop highly differentiated and cost-effective technology solutions to meet the increasing application specific needs of our foundry customers."


About MagnaChip Semiconductor

Headquartered in South Korea, MagnaChip Semiconductor is a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products for high volume consumer applications. MagnaChip Semiconductor has one of the broadest and deepest range of analog and mixed-signal semiconductor platforms in the industry, supported by its 30-year operating history, a large portfolio of registered and pending patents, and extensive engineering and manufacturing process expertise. For more information, please visit www.magnachip.com.


CONTACTS:

In the United States:
Robert Pursel
Director of Investor Relations
Tel. 408-625-1262
robert.pursel@magnachip.com
 
In Korea:
Chankeun Park
Senior Manager, Public Relations
Tel. +82-2-6903-3195
chankeun.park@magnachip.com

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